1. Field of the Invention
The present invention relates to a semiconductor wafer processing apparatus, and more particularly, to a diffusion apparatus for oxidizing or annealing a wafer used in a semiconductor device manufacturing process, and a semiconductor wafer processing apparatus utilizing a thermal CVD (Chemical Vapor Deposition) for forming, on a wafer surface, a metal film, a metal silicide film, an oxide film, a nitride film, a poly-crystalline silicon film, a dielectric film or an epitaxial silicon film or the like, and the present invention especially relates to a hot wall type single wafer or couple of wafers substrate processing type oxidizing apparatus and a single wafer or couple of wafers processing type CVD method which do not generate slip lines due to thermal stress.
2. Description of the Related Art
At present, a batch type apparatus (a vertical-type diffusion apparatus, a vertical-type CVD apparatus) is mainly used for a semiconductor thermal treatment process such as oxidization, anneal and thermal CVD. However, in order to cope with a high integration tendency of a semiconductor device, a technique for forming a very thin oxide film of about a couple of nanometers or a shallow diffusion layer, and a technique for preventing a natural oxidation are indispensable.
To meet these requirements, a single wafer or small number of wafers processing apparatus suitable for short time processing shorter than a couple of minutes is advantageous. Further, there is a merit that this single wafer or small number of wafers processing apparatus can easily cope with clustering unit or a larger diameter tendency of a wafer. On the other hand, it has been found that there is a problem in a manufacturing line in which a batch type apparatus and a single wafer or small number of wafers processing apparatus (an etching apparatus, a sputtering apparatus and so forth) are mixed in view of the fact that a semiconductor device cannot be manufactured within a short time. Therefore, a single wafer or small number of wafers processing thermal treatment apparatus becomes indispensable.
In the above described single wafer or small number of wafers processing thermal treatment apparatus, rapid heating is indispensable for improving a throughput. In that case, however, there is a problem that slip lines are generated due to thermal stress by temperature deviation within a wafer face. To cope with this problem, various methods have been studied and proposed to reduce slip lines with lamp annealing apparatus which heals a wafer at 1,000xc2x0 C. or higher within tens of seconds mainly using halogen lamp or ark lamp. Examples of such methods are shown below.
Japanese Patent Application Laid-open No.6-163444 (Conventional Art 1) discloses a technique to dispose a wafer such that an orientation flat of the wafer opposes to an opening of a guard ring, and heat the wafer using a lamp, and a technique to provide an auxiliary ring connected to opposite ends of the guard ring such as to bypass the opening of the guard ring. The wafer and the guard ring are held substantially flush with each other by a pin holder.
The above conventionally known art is for suppressing or preventing slip lines from being generated on a wafer in a lamp annealing apparatus. The lamp annealing apparatus to which this conventional art is applied has a merit that the wafer can be heated within a short time. On the other hand, as compared with the batch type thermal treatment apparatus, there are problems that uniformity of temperature of wafers is inferior, consumption of electricity is greater, and a lifetime of the lamp is short.
Japanese Patent Application Laid-open No.2-69932 (Conventional Art 2) disclosed by the present inventors discloses a semiconductor wafer thermal treatment apparatus as a single wafer or small number of wafers processing thermal treatment apparatus in which the above problems are overcome. This is a vertical-type single wafer or small number of wafers processing thermal treatment apparatus, in which a plurality of wafers are substantially vertically held on a transfer jig having function for both supporting and transferring the wafers, the wafers are inserted at a high speed into a reaction furnace provided at its lower portion with an insertion opening and a retrieving opening, and the wafers are oxidized or annealed. In the above mentioned former lamp anneal apparatus, after the wafer is inserted into a reaction furnace, the lamp is electrically conducted to start heating the wafer. Whereas, in the latter conventional apparatus, the heater is always electrically conducted to keep the reaction chamber at a high temperature (hot wall type), and the wafers are inserted at a high speed and processed. Therefore, there are merits that uniformity of temperature of wafers is excellent, consumption of electricity is small, and lifetime of the heater is long. However, as in the lamp anneal apparatus, the hot wall type single wafer or small number of wafers processing thermal treatment apparatus also has a problem that slip lines are generated due to thermal stress by temperature deviation within the wafer face. That is, since the latter conventional apparatus simultaneously processes the two wafers, the center of each of the wafers is heated only from its one side facing the heater but the edge of each of the wafers is also heated by radiation entering from clearances among wafers and therefore, temperature of the outer side of the wafer rises faster than the inner side of the wafer. In the latter conventional application, there is disclosed a technique to relatively retard the temperature rise of the wafer edge by providing rings among or outside the two wafers supported on the transfer jig.
As a CVD apparatus which keeps the merit of the above mentioned vertical-type single wafer or small number of wafers processing thermal treatment apparatus, and which makes it easy to use the apparatus as a cluster unit, there is a known single wafer or small number of wafers processing CVD apparatus for horizontally-holding a plurality of wafers for processing. This single wafer or small number of wafers processing CVD apparatus is disclosed in Japanese Patent Application Laid-open No.7-94419 (Conventional Art 3). A structure of a reaction furnace of this single wafer or small number of wafers processing CVD apparatus will be explained with reference to FIGS. 15 to 17b. FIG. 15 is a cross-sectional view of the reaction furnace of the conventional single wafer or small number of wafers processing CVD apparatus as viewed from above. FIG. 16 is a vertical cross-sectional view of the reaction furnace of the conventional single wafer or small number of wafers processing CVD apparatus as viewed side. FIGS. 17a and 17b are vertical cross-sectional views of the reaction furnace of the conventional single wafer or small number of wafers processing CVD apparatus as viewed from side for showing a supporting method of wafers in the reaction furnace. The apparatus is provided at its upper and lower portions with flat heaters 1 each divided into a plurality of zones, and a reaction tube 2 is disposed between the upper and lower heaters 1. Two wafers 3 in a horizontal state are inserted and heated. While a gas is supplied from a gas supply port 4 (4a, 4b), the gas is discharged from an exhaust port 5 (5a, 5b) disposed opposite side from the gas supply port 4 (4a, 4b) (gas flows in parallel to the wafers 3 as shown by white or black arrow in the drawings), thereby forming films on the wafers 3. Abase 20 is disposed in the reaction tube 2, and supporting plates 8a and 8b for supporting the wafers 3 thereon are provided on the base 20. The supporting plates 8a and 8b are positioned at substantially central portion of the reaction tube 2. Supporting plate holding pins 22 are provided on the base 20 at four corners of the supporting plates 8a and 8b. Each of the supporting plate holding pins 22 is formed such that its thickness is changed in two steps, i.e., the lowermost portion thereof is the thickest and the uppermost portion thereof is the thinnest. The lower supporting plate 8b is abutted and stopped against the lower step of the supporting plate holding pins, and the upper supporting plate 8a is abutted and stopped against the upper step. The supporting plates 8a and 8b are provided at their central portions with openings 84 having substantially the same shape and same size as those of the wafer 3, and the wafers 3 are held on supporting pins 82a and 82b provided around the openings 84. Two wafers 3 are placed on the transfer jigs 11 and simultaneously inserted into the reaction tube 2 through a gate valve 10a, the transfer jigs 11 are lowered at a predetermined position, and the wafers 3 are transferred onto the supporting plates 8a and 8b. For this purpose, the supporting plates 8a and 8b are provided with slits at positions thereof where the transfers jig 11 vertically pass through. Since a single wafer or small number of wafers processing oxidizing apparatus having the same shape as that of this single wafer or small number of wafers processing CVD apparatus does not use the rectangular supporting plates, a wafer is placed directly on the base 20 disposed in the reaction tube 2, and processed as shown in FIG. 18.
Influence or affection by generation of the above mentioned slip lines are not so serious in a thermal CVD process in which a wafer is processed at a relatively low temperature of 900xc2x0 C. or lower, but such influence or affection becomes serious in a process such as oxidization, anneal or epitaxial growth requiring a processing temperature of 900xc2x0 C. or higher.
This point will be explained in more detail with reference to FIGS. 19 and 20. FIG. 19 is a numerical graph showing a difference in temperature rise between wafer center and wafer edge when wafers are inserted in the reaction furnace. FIG. 20 is a numerical graph showing a temperature distribution of wafer face when the transfer jig is inserted into the reaction furnace to take out high temperature heated wafers. As shown in FIG. 19 and FIG. 20, the temperature deviation generated in the wafer face is increased when the wafers are inserted into the reaction tube and when the wafers are retrieved from the reaction tube, but main reasons of the temperature deviation are different between when the wafers are inserted and when the wafers are retrieved. FIG. 19 shows a difference in temperature rise between the wafer center and wafer edge when the wafers are inserted. In FIG. 19, the horizontal axis shows a lapse of time, and the vertical axis shows temperature. In the heating process after the wafers are inserted, the temperature rise of the wafer edge is faster than the wafer center. This is because of the following, two reasons: (1) since two wafers are simultaneously processed, the wafer center is heated from its one side, but in the case of the wafer edge, radiation enters from a clearance between the two wafers so that the wafer edge is heated from both sides, (2) since the central portion of the heater is more cooled by the inserted wafers, temperature drop around the central portion of the heater is greater than that of the wafer edge. In FIG. 20, the horizontal axis shows positions within a wafer perpendicular to the transferring direction of the wafers (the center of the wafer is 0), and the vertical axis shows temperature of wafer. FIG. 20 shows calculated result in which the wafers and the transfer jig are located in the furnace from 0 to 5 seconds, and after that, they are retrieved or taken out from the furnace. As shown in FIG. 20, while the wafers are being retrieved, the low temperature transfer jig (they are normally standing by outside the reaction furnace at a room temperature) approaches the high temperature wafers or partially contacts therewith, and the wafers are locally cooled so that a large temperature deviation is generated. As described above, it can be found that when the wafers are inserted into and retrieved from the reaction furnace, temperature difference of tens of degrees is generated in the wafer surface and the slip lines are prone to be generated at an extremely high probability.
Therefore, in order to solve the problem of generation of slip lines, or to reduce slip lines in the hot wall type single wafer or small number of wafers processing apparatus, it is important to achieve the following four points: (1) to prevent the temperature rise of wafer edge from becoming faster as compared with the wafer center when the wafers are inserted, (2) to reduce a local temperature deviation at the supporting points of the wafer when they are inserted, (3) to simultaneously prevent the temperature of wafer from being lowered locally by contact or approach of the transfer jig when the wafers are retrieved, and (4) to avoid, when the wafers are retrieved, the temperature deviation within the wafer face caused by the fact that temperature drop of the wafer edge becomes faster as compared with the wafer center contrary to the case when the wafers are inserted.
In the conventional art 3, a reduction in slip lines generated by the above described causes is not taken into account. Further, slip lines reducing methods disclosed in the other conventional arts have the following problems if they are applied to the single wafer or small number of wafers processing thermal treatment apparatus:
First, in the apparatus for holding two wafers vertically and processing the same disclosed in the conventional art 2, since the transfer jig also functions as the supporting mechanism of wafers, the transfer jig can not be retrieved out from the reaction furnace during processing of the wafers, and the reaction furnace can not be lidded. Further, the transfer jig is integrally formed with rings for the purpose of preventing the slip or is always used in a state where the transfer jig is assembled with the rings. The fact that this method can not be applied to a cluster unit which is necessary to partition the load lock chamber and the reaction furnace from each other by the gate valve or the like is not taken into account in this conventional art 2.
The technique disclosed in the conventional art 1 is for the lamp anneal apparatus in which the rings are always provided in the reaction chamber. Therefore, slip lines generated due to non-uniformity of temperature by approach or contact of the transfer jig when the wafers are inserted or retrieved, i.e., the above mentioned point 3 is not taken into account.
Thereupon, in a single wafer or couple of wafers processing thermal treatment semiconductor processing apparatus for holding the wafers substantially horizontally and processing the same, it is a main object of the present invention to provide a semiconductor processing apparatus capable of preventing slip lines from being generated in a wafer, or reducing the generation of the slip lines.
According to a first aspect of the present invention, there is provided a semiconductor wafer processing apparatus, comprising:
a reaction furnace capable of heating inside thereof;
a wafer mount for mounting a semiconductor wafer thereon, the wafer mount including an opening which is greater than the semiconductor wafer and which has a circle shape or a shape substantially similar to an outer periphery of the semiconductor wafer, and including a wafer supporting portion projecting inwardly of the opening for supporting the semiconductor wafer; and
a transfer device, for transferring the wafer mount carrying the semiconductor wafer thereon substantially horizontally into and/or out from the reaction furnace, the transfer device being capable of holding the wafer mount outside the semiconductor wafer as viewed from a vertical direction.
According to a second aspect of the present invention there is provided a method for manufacturing a semiconductor device comprising the steps of:
mounting a semiconductor wafer on a wafer mount, the wafer mount including an opening which is greater than the semiconductor wafer and which has a circle shape or a shape substantially similar to an outer periphery of the semiconductor wafer, and including a wafer supporting portion projecting inwardly of the opening for supporting the semiconductor wafer; and transferring the wafer mount by a transfer device for transferring the wafer mount carrying the semiconductor wafer thereon into and/or out from the reaction furnace, the transfer device being capable of holding the wafer mount outside the semiconductor wafer as viewed from a vertical direction;
processing the semiconductor wafer while heating the semiconductor wafer in the reaction furnace; and
forming a semiconductor device in or on the semiconductor wafer.